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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2006 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com mar?06 ds31 9 -bq pp2 cs429 9 -bq features l a c ?97 2.1 compatible l industry leading mixed signal technology l 20-bit stereo digital-to-analog converters l 18-bit stereo analog-to-digital converters l sample rate converters l four analog line-level stereo inputs for line_in, cd, video, and aux l two analog line-level mono inputs for modem and internal pc beep l dual stereo line-level outputs for line_out and alt_line_out l dual microphone inputs l high quality pseudo-differential cd input l extensive power management support l meets or exceeds the microsoft ? pc 99 audio performance requirements l s/pdif digital audio output l crystalclear ? 3d stereo enhancement l industrial temperature range description t he cs429 9 -bq is an a c ?97 2.1 compatible stereo au- dio codec designed for pc multimedia systems. using the industry leading crystalclear ? delta-sigma and mixed signal technology, the cs429 9 -bq enables the design of p c 99-compliant desktop, portable, and enter- tainment pcs. coupling the cs429 9 -bq with a pci audio accelerator or core logic supporting the ac ?97 interface, implements a cost effective, superior quality, audio solution. the cs429 9 -bq surpasses pc 99 and ac ?97 2.1 audio quality standards. ordering info cs429 9 - bqz lead-free 48-pin lqfp 9x9x1.4 mm ac '97 registers line cd aux video mic1 mic2 phone pc_beep line_out alt_line_out mono_out analog input mux and output mixer ac-link and ac '97 registers pcm_data gain / mute controls input mux output mixer mixer / mux selects ac- link pwr mgt test sync bit_clk sdata_out sdata_in reset# pcm_data src src id0# id1# eapd, s/pdif eapd spdif_out 18 bit adc 20 bit dac 3d stereo enhancement input mixer crystalclear ? soundfusion ? audio code c ?97 copyright ? cirrus logic, inc. 2006 (all rights reserved) preliminary product information this document contains information for a new product. cirrus logic reserves the right to mo dify this product without notice. http://www.cirrus.com crystalclear ? soundfusion? audio codec ?97 cs4299-bq march '06 ds319-bqpp2
cs429 9 -bq 2 table of contents 1. characteristics and specifications ........................................................................ 5 analog characteristics ................................................................................................ 5 absolute maximum ratings ........................................................................................... 6 recommended operating conditions ....................................................................... 6 digital characteristics ................................................................................................. 6 ac ?97 serial port timing ................................................................................................. 7 2. general description ..................................................................................................... 10 2.1 ac-link ............................................................................................................................ 10 2.2 control registers .............................................................................................................. 10 2.3 sample rate converters .................................................................................................. 11 2.4 output mixer .................................................................................................................... 11 2.5 input mux ......................................................................................................................... 11 2.6 volume control ................................................................................................................ 11 3. aclink frame definition ............................................................................................... 13 3.1 ac-link serial data output frame .................................................................................. 14 3.1.1 serial data output slot tags (slot 0) ............................................................................. 14 3.1.2 command address port (slot 1) .................................................................................... 15 3.1.3 command data port (slot 2) .......................................................................................... 15 3.1.4 pcm playback data (slots 3-10) ................................................................................... 15 3.2 ac-link audio input frame .............................................................................................. 16 3.2.1 serial data input slot tag bits (slot 0) ......................................................................... 16 3.2.2 status address port (slot 1) .......................................................................................... 16 3.2.3 status data port (slot 2) ................................................................................................ 17 3.2.4 pcm capture data (slot 3-10) ....................................................................................... 17 3.3 ac-link protocol violation - loss of sync ..................................................................... 18 4. register interface ........................................................................................................ 19 4.1 reset register (index 00h) .............................................................................................. 20 4.2 master volume register (index 02h) ............................................................................... 20 4.3 alternate volume register (index 04h) ............................................................................ 21 4.4 mono volume register (index 06h) ................................................................................. 21 4.5 pc_beep volume register (index 0ah) ......................................................................... 22 4.6 phone volume register (index 0ch) ................................................................................ 22 4.7 microphone volume register (index 0eh) ........................................................................ 23 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm microsoft is a registered trademark of microsoft corporation in the united states and/or other countries. intel is a registered trademark of intel corporation. crystal clear and sound fusion are trademarks of cirrus logic. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyri ghts, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, pho- tographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk ma y be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec- tronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of t his publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cir rus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered i n some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com. 2 ds319-bqpp2 cs4299-bq
cs429 9 -bq 3 4.8 stereo analog mixer input gain registers (index 10h - 18h) ........................................... 24 4.9 input mux select register (index 1ah) ............................................................................. 25 4.10 record gain register (index 1ch) ................................................................................. 25 4.11 general purpose register (index 20h) ........................................................................... 26 4.12 3d control register (index 22h) ..................................................................................... 26 4.13 powerdown control/status register (index 26h) ........................................................... 27 4.14 extended audio id register (index 28h) ........................................................................ 28 4.15 extended audio status/control register (index 2ah) .................................................... 28 4.16 pcm front dac rate register (index 2ch) ................................................................ 29 4.17 pcm l/r adc rate register (index 32h) ...................................................................... 29 4.18 ac mode control register (index 5eh) .......................................................................... 30 4.19 misc. crystal control register (index 60h) ..................................................................... 30 4.20 s/pdif control register (index 68h) ............................................................................. 31 4.21 vendor id1 register (index 7ch) ................................................................................... 32 4.22 vendor id2 register (index 7eh) ................................................................................... 32 5. power management ....................................................................................................... 33 5.1 ac?97 reset modes ........................................................................................................ 33 5.1.1 cold ac?97 reset .............................................................................................. 33 5.1.2 warm ac?97 reset ............................................................................................ 33 5.1.3 register ac?97 reset ........................................................................................ 33 5.2 powerdown controls ....................................................................................................... 34 6. analog hardware description ................................................................................. 36 6.1 analog inputs ................................................................................................................... 36 6.1.1 line-level inputs ................................................................................................. 36 6.1.2 cd input .............................................................................................................. 36 6.1.3 microphone inputs .............................................................................................. 37 6.1.4 pc beep input ..................................................................................................... 37 6.1.5 phone input ......................................................................................................... 38 6.2 analog outputs ................................................................................................................ 38 6.2.1 stereo outputs .................................................................................................... 38 6.2.2 mono output ....................................................................................................... 38 6.3 miscellaneous analog signals ......................................................................................... 39 6.4 power supplies ................................................................................................................ 39 6.5 reference design ............................................................................................................ 39 7. sony/philips digital interface (s/pdif) ................................................................... 40 8. grounding and layout ................................................................................................. 40 9. pin descriptions ........................................................................................................... 42 10. parameter and term definitions ............................................................................ 47 11. reference design ....................................................................................................... 49 12. references ...................................................................................................................... 50 13. package dimensions .................................................................................................... 51 ds319-bqpp2 3 cs4299-bq
cs429 9 -bq 4 list of figures figure 1. power up timing .............................................................................................................. 8 figure 2. codec ready from startup or fault condition ................................................................. 8 figure 3. clocks .............................................................................................................................. 8 figure 4. data setup and hold ........................................................................................................ 9 figure 5. pr4 powerdown and warm reset .................................................................................. 9 figure 6. test mode ........................................................................................................................ 9 figure 7. ac-link connections ....................................................................................................... 10 figure 8. mixer diagram ................................................................................................................ 12 figure 9. ac-link input and output framing .................................................................................. 13 figure 10. line input (replicate for video and aux) ..................................................................... 36 figure 11. differential 2 vrms cd input ...................................................................................... 36 figure 12. differential 1 vrms cd input ...................................................................................... 36 figure 13. microphone input ......................................................................................................... 37 figure 14. microphone pre-amplifier ............................................................................................. 37 figure 15. pc_beep input ............................................................................................................ 37 figure 16. modem connection ...................................................................................................... 38 figure 17. alternate line output as headphone output ............................................................... 38 figure 18. stereo output ............................................................................................................... 38 figure 19. voltage regulator ........................................................................................................ 39 figure 20. s/pdif output .............................................................................................................. 40 figure 21. conceptual layout for the cs4299-bq ........................................................................ 41 figure 22. pin locations for the cs4299-bq ................................................................................ 42 figure 23. cs4299 reference design .......................................................................................... 49 list of tables table 1. mixer registers ...................................................................................................................... 19 table 2. analog mixer output attenuation ........................................................................................... 21 table 3. microphone input gain values .............................................................................................. 23 table 4. analog mixer input gain values ............................................................................................ 24 table 5. stereo volume register index ............................................................................................... 24 table 6. input mux selection ............................................................................................................... 25 table 7. standard sample rates ......................................................................................................... 29 table 8. slot mapping ......................................................................................................................... 30 table 9. device id with corresponding part number .......................................................................... 32 table 10. revision values ................................................................................................................... 32 table 11. powerdown pr bit functions .............................................................................................. 34 table 12. powerdown pr function matrix .......................................................................................... 35 table 13. power consumption by powerdown mode .......................................................................... 35 4 ds319-bqpp2 cs4299-bq
cs429 9 -bq 5 1. characteristics and specifications analog characteristics standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v 5%, dvdd = 3.3 v 5%; 1 khz input sine wave; sample frequency, fs = 48 khz; z al =100k ?/ 1000pf load, c dl = 18 pf load (note 1); measurement bandwidth is 20 hz - 20khz, 18-bit linear coding for adc functions, 20-bit linear coding for dac functions; mixer registers set for unity gain. notes: 1. z al refers to the analog output pin loading and c dl refers to the digital output pin loading. 2. parameter definitions are given in the section10 , parameter and term definitions . 3. path refers to the signal path used to generate this data. these paths are defined in the section10 , parameter and term definitions . 4. this specification is guaranteed by silicon characterization, it is not production tested. parameter (note 2) symbol path (note 3) CS4299-BQZ unit min typ max full scale input voltage line inputs mic inputs mic inputs (20 dbinternal gain) a-d a-d a-d - - - 1.00 1.00 0.10 - - - v rms v rms v rms full scale output voltage line,alternate line, and mono outputs d-a 0.85 1.0 1.15 v rms frequency response (note 4) analog ac = 0.25 db dac ac = 0.25 db adc ac = 0.25 db fr a-a d-a a-d 20 20 20 - - - 20,000 20,000 20,000 hz hz hz dynamic range stereo analog inputs to line_out mono analog inputs to line_out dac dynamic range adc dynamic range dr a-a a-a d-a a-d - - - - 90 85 85 80 - - - - db fs a db fs a db fs a db fs a dac snr (-20 db fs input w/ ccir-rms filter on output) snr d-a - 70 - db total harmonic distortion + noise (-3 db fs input signal): line/alternate line output dac adc (all inputs except phone/mic) adc (phone/mic) thd+n a-a d-a a-d a-d - - - - -72 -72 -72 -72 - - - - db fs db fs db fs db fs power supply rejection ratio (1khz, 0.5 v rms w/ 5 v dc offset) (note 4) - 40 - db interchannel isolation - 60 - db spurious tone (note 4) - -100 - db fs input impedance (note 4) 10 - - k ? external load impedance 10 - - k ? output impedance (note 4) - 730 - ? input capacitance (note 4) - 5 - pf vrefout 2.0 2.28 2.5 v ds319-bqpp2 5 cs4299-bq
cs429 9 -bq 6 absolute maximum ratings (avss1 = avss2 = dvss1 = dvss2 = 0 v) recommended operating conditions (avss1 = avss2 = dvss1 = dvss2 = 0 v) digital characteristics (avss = dvss = 0 v) parameter min typ max unit power supplies digital analog -0.3 -0.3 - - 5.5 5.5 v v total power dissipation (supplies, inputs, outputs) - 0.95 1.25 w input current per pin (except supply pins) -10 - 10 ma output current per pin (except supply pins) -15 - 15 ma analog input voltage -0.3 - avdd + 0.3 v digital input voltage -0.3 - dvdd + 0.3 v ambient temperature (power applied) -40 - 85 c storage temperature -65 - 150 c parameter symbol min typ max unit power supplies +3.3 v digital +5 v digital analog dvdd1, dvdd2 dvdd1, dvdd2 avdd1, avdd2 3.135 4.75 4.75 3.3 5 5 3.465 5.25 5.25 v v v operating ambient temperature -40 - 85 c parameter symbol min typ max unit low level input voltage v il - - 0.8 v high level input voltage v ih 0. 65 x dvdd - - v high level output voltage v oh 0. 9 0 x dvdd 0.99 x dvdd - v low level output voltage v ol - 0.03 0.10 x dvdd v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current bit_clk, s/pdif_out sdata_in, eapd (note 4) - - 24 4 - - ma ma 6 ds319-bqpp2 cs4299-bq
cs429 9 -bq 7 ac ?97 serial port timing standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v, dvdd = 3.3 v; c l = 55pf load. parameter symbol min typ max unit reset timing reset# active low pulse width t rst_low 1.0 - - s reset# inactive to bit_clk start-up delay t rst2clk - 40.0 - s 1st sync active to codec ready set t sync2crd - 62.5 - s vdd stable to reset inactive t vdd2rst# 100 - - s clocks bit_clk frequency f clk - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter (depends on xtal_in source) - - 750 ps bit_clk high pulse width t clk_high 36 40.7 45 ns bit_clk low pulse width t clk_low 36 40.7 45 ns sync frequency f sync - 48 - khz sync period t sync_period - 20.8 - s sync high pulse width t sync_high - 1.3 - s sync low pulse width t sync_low - 19.5 - s data setup and hold output propagation delay from rising edge of bit_clk t co - 12 - ns input setup time from falling edge of bit_clk t isetup 10 - - ns input hold time from falling edge of bit_clk t ihold 0 - - ns input signal rise time t irise 2 - 6 ns input signal fall time t ifall 2 - 6 ns output signal rise time (note 4) t orise 2 4 6 ns output signal fall time (note 4) t ofall 2 4 6 ns misc. timing parameters end of slot 2 to bit_clk, sdata_in low (pr4) t s2_pdown - .28 1.0 s sync pulse width (pr4) warm reset t sync_pr4 1.0 - - s sync inactive (pr4) to bit_clk start-up delay t sync2clk 162.8 285 - ns setup to trailing edge of reset# (ate test mode) (note 4) t setup2rst 15 - - ns rising edge of reset# to hi-z delay (note 4) t off - - 25 ns ds319-bqpp2 7 cs4299-bq
cs429 9 -bq 8 b i t _ c l k t r s t _ l o w t r s t 2 c l k t v d d 2 r s t # v d d r e s e t # figure 1. power up timing figure 2. codec ready from startup or fault condition b i t _ c l k t s y n c 2 c r d c o d e c _ r e a d y s y n c figure 3. clocks b i t _ c l k s y n c t i r i s e t i f a l l t o r i s e t i f a l l t c l k _ h i g h t c l k _ l o w t s y n c _ h i g h t s y n c _ l o w t s y n c _ p e r i o d t c l k _ p e r i o d 8 ds319-bqpp2 cs4299-bq
cs429 9 -bq 9 b i t _ c l k t i s e t u p t i h o l d t c o s d a t a _ o u t , s y n c s d a t a _ i n figure 4. data setup and hold b i t _ c l k t s 2 _ p d o w n s d a t a _ i n s d a t a _ o u t s y n c w r i t e t o 0 x 2 0 d a t a p r 4 d o n ' t c a r e s l o t 1 s l o t 2 s y n c _ p r 4 s y n c 2 c l k t t figure 5. pr4 powerdown and warm reset r e s e t # s d a t a _ o u t , s y n c t s e t u p 2 r s t s d a t a _ i n , t o f f b i t _ c l k h i - z figure 6. test mode ds319-bqpp2 9 cs4299-bq
cs429 9 -bq 10 2. general description the cs429 9 -bq is a mixed-signal serial audio co- dec compliant to the intel ? audio codec ?97 spec- ification , revision 2.1 [1]. it is designed to be paired with a digital controller, typically located on the pci bus or integrated within the system core logic chip set. the controller is responsible for all com- munications between the cs429 9 -bq and the re- mainder of the system. the cs429 9 -bq contains two distinct functional sections: digital and analog. the digital section includes the ac-link interface, s/pdif interface, serial data port , sample rate converters , and power management support. the analog section includes the analog input multiplex- er (mux), stereo output mixer, mono output mixer, stereo analog-to-digital converters (adcs), ste- reo digital-to-analog converters (dacs), and their associated volume controls. 2.1 ac-link all communication with the cs429 9 -bq is estab- lished with a 5-wire digital interface to the control- ler, as shown in figure7. this interface is called the ac-link. all clocking for the serial communi- cation is synchronous to the bit_clk signal. bit_clk is generated by the primary audio codec and is used to clock the controller and any second- ary audio codecs. both input and output ac-link audio frames are organized as a sequence of 256 se- rial bits forming 13 groups referred to as ?slots?. during each audio frame, data is passed bi-direc- tionally between the cs429 9 -bq and the control- ler. the input frame is driven from the cs429 9 -bq on the sdata_in line. the output frame is driven from the controller on the sdata_out line. the controller is also responsible for issuing reset com- mands via the reset# signal. following a cold reset, the cs429 9 -bq is responsible for notifying the controller that it is ready for operation after syn- chronizing its internal functions. the cs429 9 -bq ac-link signals must use the same digital supply voltage as the controller chip, either +5 v or +3.3v. see section3, aclink frame definition , for detailed ac-link information. 2.2 control registers the cs429 9 -bq contains a set of ac ?97 compli- ant control registers and a set of cirrus logic de- fined control registers. these registers control the basic functions and features of the cs429 9 -bq . read accesses of the control registers by the ac?97 controller are accomplished with the re- quested register index in slot1 of a sdata_out frame. the following sdata_in frame will con- c o d e c s y n c b i t _ c l k s d a t a _ o u t s d a t a _ i n r e s e t # d i g i t a l a c ' 9 7 c o n t r o l l e r figure 7. ac-link connections 10 ds319-bqpp2 cs4299-bq
cs429 9 -bq 11 tain the read data in its slot 2. write operations are similar, with the register index in slot 1 and the write data in slot 2 of a sdata_out frame. the function of each input and output frame is detailed in section3, aclink frame definition . individual register descriptions are found in section4, regis- ter interface . 2.3 sample rate converters the sample rate converters (srcs) provide high accuracy digital filters supporting sample frequen- cies other than 48khz to be captured from the cs4299 or played from the controller. ac ?97 re- quires support for two audio rates (44.1 and 48khz). in addition, the intel ? i/o controller hub (ichx) specification requires support for five more audio rates (8, 11.025, 16, 22.05, and 32). the cs4299 supports all these rate, as shown in table7 on page29. 2.4 output mixer the cs429 9 -bq has two output mixers, illustrated in figure8. the stereo output mixer sums together the analog inputs to the cs429 9 -bq , including the pc_beep and phone signals, according to the settings in the volume control registers. the stereo output mix is sent to the line_out and alt_line_out pins on the cs429 9 -bq . the mono output mixer generates a monophonic sum of the left and right channels from the stereo input mixer. the mono output mix is sent to the mono_out output pin on the cs429 9 -bq . 2.5 input mux the input multiplexer controls which analog input is sent to the adcs. the output of the input mux is converted to stereo 18-bit digital pcm data and sent to the controller by means of the ac-link sdata_in signal. 2.6 volume control the cs429 9 -bq volume registers control analog input levels to the input mixer and analog output levels, including the master volume level, and the alternate volume level. the pc_beep volume con- trol uses 3db steps with a range of 0db to -45db attenuation. all other analog volume controls use 1.5db steps. the analog inputs have a mixing range of +12db signal gain to -34.5db signal at- tenuation. the analog output volume controls have from 0db to -94.5db attenuation for line_out and from 0db to -46.5db attenuation for alt_line_out and mono_out. ds319-bqpp2 11 cs4299-bq
cs429 9 -bq 12 vol mute vol mute vol mute vol vol mute vol vol vol mute boost 1/2 output buffer output buffer output buffer vol vol adc input mux vol adc mute pcm_out pc_beep phone mic1 mic2 line cd video aux analog stereo input mixer analog stereo output mixer master volume alt line volume mono volume mono out select stereo to mono mixer main adc gain main a/d converters mic select mono out line out pcm_in dac main d/a converters 1/2 stereo to mono mixer mute mute mute 3d alt line out 3d output mixer vol mute mute mute dac direct mode pc beep bypass bypass buffer figure 8. mixer diagram 12 ds319-bqpp2 cs4299-bq
cs429 9 -bq 13 3. aclink frame definition the ac-link is a bidirectional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. the first slot, called the tag slot, contains bits indicating if the cs429 9 -bq is ready to receive data (input frame) and which, if any, other slots contain valid data. slots 1 through 12 contain audio or con- trol/status data. both the serial data output and in- put frames are defined from the controller perspective, not from the cs429 9 -bq perspective. the controller synchronizes the beginning of a frame with the assertion of the sync signal. figure9 shows the position of each bit location within the frame. the first bit position in a new se- rial data frame is f0 and the last bit position in the serial data frame is f255. when sync goes active (high) and is sampled active by the cs429 9 -bq (on the falling edge of bit_clk), both devices are synchronized to a new serial data frame. the data on the sdata_out pin at this clock edge is the final bit of the previous frame?s serial data. on the next rising edge of bit_clk, the first bit of slot0 is driven by the controller on the sdata_out pin. on the next falling edge of bit_clk, the cs429 9 -bq latches this data in, as the first bit of the frame. 20.8 s (48 khz) tag phase data phase 12.288 mhz 81.4 ns sync bit_clk sdata_out sdata_in f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 d19 f255 valid frame slot 1 valid 0 r/w 0 wd15 f36 f57 d19 d18 d19 d19 d18 d19 rd15 0 0 0 0 f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 f255 f36 f57 f255 f255 0 0 gpio int f96 f96 d19 slot 0 slot 1 slot 2 slot 3 slot 4 slots 5-12 slot 2 valid slot 1 valid slot 2 valid codec ready 0 slot 12 valid codec id1 codec id0 slot 12 valid gpio int bit frame position: bit frame position: figure 9. ac-link input and output framing ds319-bqpp2 13 cs4299-bq
cs429 9 -bq 14 3.1 ac-link serial data output frame in the serial data output frame, data is passed on the sdata_out pin to the cs429 9 -bq from the ac ?97 controller. figure9 illustrates the serial port timing. the pcm playback data being passed to the cs429 9 -bq is shifted out msb first in the most significant bits of each slot. any pcm data from the ac ?97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions. bits that are reserved should always be ?cleared? by the ac ?97 controller. 3.1.1 serial data output slot tags (slot 0) valid frame the valid frame bit determines if any of the following slots contain either valid playback data for the cs429 9 -bq dacs or data for read/write operations. when ?set?, at least one of the other ac-link slots contain valid data. if this bit is ?clear?, the remainder of the frame is ignored. slot [1:2] valid the slot [1:2] valid bits indicate the validity of data in their corresponding serial data output slots. if a bit is ?set?, the corresponding output slot contains valid data. if a bit is ?cleared?, the corresponding slot will be ignored. slot [3:10] valid the slot [3:10] valid bits indicate slot [3:10] contains valid playback data for the cs429 9 -bq . if a slot valid bit is ?set?, the named slot contains valid audio data. if the bit is ?clear?, the slot will be ignored. the cs429 9 -bq supports alternate slot mapping as defined in the ac ?97 2.1 spec- ification. for more information, see the ac mode control register (index 5eh) . codec id[1:0] the codec id[1:0] bits display the codec id of the audio codec being accessed during the cur- rent ac-link frame. codecid[1:0]= 00 indicates the primary codec is being accessed. codec id[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. a non-zero value of one or more of the codec id bits indicates a valid read or write address in slot 1, and the slot 1 r/w bit indicates presence or absence of valid data in slot 2. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 valid frame slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid reserved codec id1 codec id0 14 ds319-bqpp2 cs4299-bq
cs429 9 -bq 15 3.1.2 command address port (slot 1) r/ w read/ write . when this bit is ?set?, a read of the ac ?97 register specified by the register index bits will occur in the ac ?97 2.1 audio codec. when the bit is ?cleared?, a write will occur. for any read or write access to occur, the frame valid bit (f0) must be ?set? and the codec id[1:0] bits (f[14:15]) must match the codec id of the ac ?97 2.1 audio codec being accessed. additionally, for a primary codec, the slot 1 valid bit (f1) must be ?set? for a read access and both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be ?set? for a write access. for a secondary co- dec, both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be ?cleared? for read and write accesses. see figure9 for bit frame positions. ri[6:0] register index. the ri[6:0] bits contain the 7-bit register index to the ac ?97 registers in the cs429 9 -bq . all registers are defined at word addressable boundaries. the ri0 bit must be ?clear? to access cs429 9 -bq registers. 3.1.3 command data port (slot 2) wd[15:0] write data. the wd[15:0] bits contain the 16-bit value to be written to the register. if an access is a read, this slot is ignored. note: for any write to an ac ?97 register, the write is defined to be an ?atomic? access. this means that when the slot 1 valid bit in output slot 0 is ?set?, the slot 2 valid bit in output slot 0 should always be ?set? during the same audio frame. no write access may be split across 2 frames. 3.1.4 pcm playback data (slots 3-10) pd[19:0] playback data. the pd[19:0] bits contain the 20-bit pcm playback (2?s complement) data for the left and right dacs and/or the s/pdif transmitter. table8 on page30 lists a cross reference for each function and its respective slot. the mapping of a given slot to a dac is determined by the state of the id[1:0] bits in the extended audio id register (index 28h) and by the sm[1:0] and amap bits in the ac mode control register (index 5eh). bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/ w ri6 ri5 ri4 ri3 ri2 ri1 ri0 0 0 0 0 0 0 0 0 0 0 0 0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 reserved bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ds319-bqpp2 15 cs4299-bq
cs429 9 -bq 16 3.2 ac-link audio input frame in the serial data input frame, data is passed on the sdata_in pin from the cs429 9 -bq to the ac?97 controller. the data format for the input frame is very similar to the output frame. figure9 on page13 il- lustrates the serial port timing. the pcm capture data from the cs429 9 -bq is shifted out msb first in the most significant 18 bits of each slot. the least significant 2 bits in each slot will be ?cleared?. if the host requests pcm data from the ac?97 controller that is less than 18 bits wide, the controller should dither and round or just round (but not truncate) to the desired bit depth. bits that are reserved or not implemented in the cs429 9 -bq will always be returned ?cleared?. 3.2.1 serial data input slot tag bits (slot 0) codec ready the codec ready bit indicates the readiness of the cs429 9 -bq ac-link. immediately after a cold reset this bit will be ?clear?. once the cs429 9 -bq clocks and voltages are stable, this bit will be ?set?. until the codec ready bit is ?set?, no ac-link transactions should be attempted by the controller. the codec ready bit does not indicate readiness of the dacs, adcs, vref, or any other analog function. those must be checked in the powerdown control/status reg- ister (index 26h) by the controller before any access is made to the mixer registers. any ac- cesses to the cs429 9 -bq while codec ready is ?clear? are ignored. slot 1 valid when ?set?, the slot 1 valid bit indicates slot 1 contains a valid read back address. slot 2 valid when ?set?, the slot 2 valid bit indicates slot 2 contains valid register read data. slot [3:10] valid when ?set?, the slot [3:10] valid bits indicate slot [3:10] contains valid capture data from the cs429 9 -bq adcs. only if a slot [3:10] valid bit is ?set? will the corresponding input slot con- tain valid data. 3.2.2 status address port (slot 1) ri[6:0] register index. the ri[6:0] bits echo the ac?97 register address when a register read has been requested in the previous frame. the cs429 9 -bq will only echo the register index for a read access. write accesses will not return valid data in slot 1. sr[3:10] slot request. if srx is ?set?, this indicates the cs4299 src does not need a new sample on the next ac-link frame for that particular slot. if srx is ?clear?, the src indicates a new sample is needed on the following frame. if the vra bit in the extended audio status/control register (index 2ah) is ?clear?, the sr[3:10] bits are always 0. when vra is ?set?, the src is enabled and the sr[3:10] bits are used to request data. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 codec ready slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid 0 0 0 0 0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ri6 ri5 ri4 ri3 ri2 ri1 ri0 sr3 sr4 sr5 sr6 sr7 sr8 sr9 sr10 0 reserved 16 ds319-bqpp2 cs4299-bq
cs429 9 -bq 17 3.2.3 status data port (slot 2) rd[15:0] read data. the rd[15:0] bits contain the register data requested by the controller from the previous read request. all read requests will return the read address in the input slot 1 and the register data in the input slot 2 on the following serial data frame. 3.2.4 pcm capture data (slot 3-10) cd[17:0] capture data. the d[17:0] bits contain 18-bit pcm (2?s complement) capture data. the map- ping of a given slot to an adc is determined by the state of the id[1:0] bits in the extended audio id register (index 28h) and the sm[1:0] and amap bits in the ac mode control reg- ister (index 5eh). the definition of each slot can be found in table8 on page30. bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 reserved bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 0 0 ds319-bqpp2 17 cs4299-bq
cs429 9 -bq 18 3.3 ac-link protocol violation - loss of sync the cs429 9 -bq is designed to handle sync pro- tocol violations. the following are situations where the sync protocol has been violated: ? the sync signal is not sampled high for exact- ly 16 bit_clk clock cycles at the start of an audio frame. ? the sync signal is not sampled high on the 256th bit_clk clock period after the previous sync assertion. ? the sync signal goes active high before the 256th bit_clk clock period after the previous sync assertion. upon loss of synchronization with the controller, the cs429 9 -bq will ?clear? the codec ready bit in the serial data input frame until two valid frames are detected. during this detection period, the cs429 9 -bq will ignore all register reads and writes and will discontinue the transmission of pcm capture data. in addition, if the losm bit in the misc. crystal control register (index 60h) is ?set? (default), the cs429 9 -bq will mute all analog outputs. if the losm bit is ?clear?, the analog out- puts will not be muted. 18 ds319-bqpp2 cs4299-bq
cs429 9 -bq 19 4. register interface reg register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 se4 se3 se2 se1 se0 0 id8 id7 0 0 id4 0 0 0 0 1990h 02h master volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h alternate volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h mono volume mute 0 0 0 0 0 0 0 0 0 mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 0000h 0ch phone volume mute 0 0 0 0 0 0 0 0 0 0 gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute 0 0 0 0 0 0 0 0 20db 0 gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 1ah record select 0 0 0 0 0 sl2 sl1 sl0 0 0 0 0 0 sr2 sr1 sr0 0000h 1ch record gain mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 8000h 20h general purpose 0 0 3d 0 0 0 mix ms lpbk 0 0 0 0 0 0 0 0000h 22h 3d control 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc 000fh 28h extended audio id id1 id0 0 0 0 0 amap 0 0 0 0 0 0 0 0 vra 0201h 2ah extended audio ctrl/stat 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vra 0000h 2ch pcm front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm l/r adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h cirrus logic defined registers : 5e ac mode control 0 0 0 0 0 0 0 ddm amap 0 sm1 sm0 0 0 0 0 0080h 60 misc. crystal control 0 0 0 0 reserved 0 0 reserved 0 reserved losm 0023h 68 s/pdif control spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro 0000h 7ch vendor id1(cr) f7 f6 f5 f4 f3 f4 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4352h 7eh vendor id2(y-) t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 0 rev2 rev1 rev0 5931h table 1. mixer registers ds319-bqpp2 19 cs4299-bq
cs429 9 -bq 20 4.1 reset register (index 00h) se[4:0] crystal 3d stereo enhancement. se[4:0] = 00110, indicating this feature is present. id8 18-bit adc resolution. the id8 bit is ?set?, indicating this feature is present. id7 20-bit dac resolution. the id7 bit is ?set?, indicating this feature is present. id4 headphone output (alt line out). the id4 bit is ?set?, indicating this feature is present. default 1990h. the data in this register is read-only data. any write to this register causes a register reset to the default state of the audio (index 00h - 38h) and vendor spe- cific (index 5ah - 7ah) registers . a read from this register returns configuration information about the cs429. 4.2 master volume register (index 02h) mute master mute. setting this bit mutes the line_out_l/r output signals. ml[5:0] master volume left. these bits control the left master output volume. each step corresponds to 1.5 db gain adjustment, with 00000 = 0db. the total range is 0 db to -94.5db attenuation. mr[5:0] master volume right. these bits control the right master output volume. each step corresponds to 1.5 db gain adjustment, with 00000 = 0 db. the total range is 0 db to -94.5db attenuation. default 8000h. this value corresponds to 0 db attenuation and mute ?set?. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 se4 se3 se2 se1 se0 0 id8 id7 0 0 id4 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 20 ds319-bqpp2 cs4299-bq
cs429 9 -bq 21 4.3 alternate volume register (index 04h) mute alternate mute. setting this bit mutes the alt_line_out_l/r output signals. ml[4:0] alternate volume left. these bits control the left alternate output volume. each step corre- sponds to 1.5db gain adjustment, with 00000 = 0db. the total range is 0 db to -46.5db atten- uation. see table2 for further attenuation levels. ml5 alternate volume left max attenuation. setting ml5 sets the left channel attenuation to -46.5db by forcing ml[4:0] to a ?1? state. ml[5:0] will read back 011111 when ml5 has been ?set?. table2 summarizes this behavior. mr[4:0] alternate volume right. these bits control the right alternate output volume. each step corre- sponds to 1.5db gain adjustment, with 00000 = 0db. the total range is 0 db to -46.5db atten- uation. see table2 for further attenuation levels. mr5 alternate volume right max attenuation. setting mr5 sets the right channel attenuation to -46.5db by forcing mr[4:0] to a ?1? state. mr[5:0] will read back 011111 when mr5 has been ?set?. table2 summarizes this behavior. default 8000h. this value corresponds to 0 db attenuation and mute ?set?. 4.4 mono volume register (index 06h) mute mono mute. setting this bit mutes the mono_out signal. mm[5:0] mono volume. these bits control the mono output volume. each step corresponds to 1.5 db gain adjustment, with a total available range from 0 db to -46.5 db attenuation. see table2 for further attenuation levels. mm5 mono volume max attenuation. setting the mm5 bit sets the mono attenuation to -46.5db by forcing mm[4:0] to a ?1? state. mm[5:0] will read back 011111 when mm5 has been ?set?. table2 summarizes this behavior. default 8000h. this value corresponds to 0 db attenuation and mute ?set?. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 mx[5:0] write mx[5:0] read gain level 000000 000000 0 db 000001 000001 -1.5 db ? ? ... 011111 011111 -46.5 db 100000 011111 -46.5 db ... ... ... 111111 011111 -46.5 db table 2. analog mixer output attenuation d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 0 mm5 mm4 mm3 mm2 mm1 mm0 ds319-bqpp2 21 cs4299-bq
cs429 9 -bq 22 4.5 pc_beep volume register (index 0ah) mute pc_beep mute. setting this bit mutes the pc_beep input signal. pv[3:0] pc_beep volume control. the pv[3:0] bits are used to control the gain levels of the pc_beep input source to the input mixer. each step corresponds to 3db gain adjustment, with 0000=0db. the total range is 0db to -45db attenuation. default 0000h. this value corresponds to 0 db attenuation and mute ?clear?. this register has no effect on the pc_beep volume during reset#. 4.6 phone volume register (index 0ch) mute phone mute. setting this bit mutes the phone input signal. gn[4:0] phone volume control. the gn[4:0] bits are used to control the gain levels of the phone input source to the input mixer. each step corresponds to 1.5db gain adjustment, with 01000=0db. the total range is +12 db to -34.5db gain. see table4 on page24 for further details. default 8008h. this value corresponds to 0 db gain and mute ?set?. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 0 0 gn4 gn3 gn2 gn1 gn0 22 ds319-bqpp2 cs4299-bq
cs429 9 -bq 23 4.7 microphone volume register (index 0eh) mute microphone mute. setting this bit mutes the mic1 or mic2 signal. the selection of the mic1 or mic2 input pin is controlled by the ms bit in the general purpose register (index 20h) . gn[4:0] microphone volume control. the gn[4:0] bits are used to control the gain level of the micro- phone input source to the input mixer. each step corresponds to 1.5db gain adjustment, with 01000=0db. the total range is +12 db to -34.5db gain. see table3 for further details. 20db microphone 20 db boost. when ?set?, the 20db bit enables the +20 db microphone boost block. this bit allows for variable boost of 0 db or +20 db. table3 summarizes this behavior. default 8008h. this value corresponds to 0 db gain and mute ?set?. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 20db 0 gn4 gn3 gn2 gn1 gn0 gn[4:0] gain level 20db = 0 20db = 1 00000 +12.0 db +32.0 db 00001 +10.5 db +30.5 db ? ? ... 00111 +1.5 db +21.5 db 01000 0.0 db +20.0 db 01001 -1.5 db +18.5 db ? ? ... 11111 -34.5 db -14.5 db table 3. microphone input gain values ds319-bqpp2 23 cs4299-bq
cs429 9 -bq 24 4.8 stereo analog mixer input gain registers (index 10h - 18h) mute stereo input mute. setting this bit mutes the respective input signal, both right and left inputs. gl[4:0] left volume control. the gl[4:0] bits are used to control the gain level of the left analog input source to the input mixer. each step corresponds to 1.5db gain adjustment, with 01000=0db. the total range is +12 db to -34.5db gain. see table4 for further details. gr[4:0] right volume control. the gr[4:0] bits are used to control the gain level of the right analog in- put source to the input mixer. each step corresponds to 1.5db gain adjustment, with 01000= 0db. the total range is +12 db to -34.5db gain. see table4 for further details. default 8808h. this value corresponds to 0 db gain and mute ?set?. the stereo analog mixer input gain registers are listed in table5. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 gx[4:0] gain level 00000 +12.0 db 00001 +10.5 db ? ? 00111 +1.5 db 01000 0.0 db 01001 -1.5 db ? ? 11111 -34.5 db table 4. analog mixer input gain values register index function 10h line in volume 12h cd volume 14h video volume 16h aux volume 18h pcm out volume table 5. stereo volume register index 24 ds319-bqpp2 cs4299-bq
cs429 9 -bq 25 4.9 input mux select register (index 1ah) sl[2:0] left channel source. the sl[2:0] bits select the left channel source to pass to the adcs for recording. see table6 for possible values. sr[2:0] right channel source. the sr[2:0] bits select the right channel source to pass to the adcs for recording. see table6 for possible values. default 0000h. this value selects the mic input for both channels. 4.10 record gain register (index 1ch) mute record gain mute. setting this bit mutes the input to the l/r adcs. gl[3:0] left adc gain. the gl[3:0] bits control the input gain on the left channel of the analog source, applied after the input mux and before the adcs. each step corresponds to 1.5db gain adjust- ment, with 0000 = 0db. the total range is 0 db to +22.5db gain. gr[3:0] right adc gain. the gr[3:0] bits control the input gain on the right channel of the analog source, applied after the input mux and before the adcs. each step corresponds to 1.5db gain adjustment, with 0000 = 0db. the total range is 0 db to +22.5db gain. default 8000h. this value corresponds to 0 db gain and mute ?set?. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 sl2 sl1 sl0 0 0 0 0 0 sr2 sr1 sr0 sx[2:0] record source 000 mic 001 cd input 010 video input 011 aux input 100 line input 101 stereo mix 110 mono mix 111 phone input table 6. input mux selection d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 ds319-bqpp2 25 cs4299-bq
cs429 9 -bq 26 4.11 general purpose register (index 20h) 3d 3d enable. when ?set?, the 3d bit enables the crystalclear tm 3d stereo enhancement. this function is not available in dac direct mode (ddm). mix mono output select. the mix bit selects the source for the mono out output. when ?set?, the microphone input is selected. when ?clear?, the stereo-to-mono mixer is selected. ms microphone select. the ms bit determines which of the two mic inputs are passed to the mixer. when ?set?, the mic2 input is selected. when ?clear?, the mic1 input is selected. lpbk loopback enable. when ?set?, the lpbk bit enables the adc/dac loopback mode. this bit routes the output of the adcs to the input of the dacs without involving the ac-link. default 0000h 4.12 3d control register (index 22h) s[3:0] spacial enhancement depth. these bits control the amount of ?space? added to the output ste- reo signal. when s[3:0] = 0000, the minimum amount of spatial enhancement is added. when s[3:0] = 1111, the maximum amount of spatial enhancement is added. the 3d function is en- abled and disabled by the 3d bit in the general purpose register (index 20h) . default 0000h. this value corresponds to minimum spatial enhancement added to the output signal. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 3d 0 0 0 mix ms lpbk 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0
cs429 9 -bq 27 4.13 powerdown control/status register (index 26h) eapd external amplifier power down. the eapd pin follows this bit and is generally used to power down external amplifiers. pr6 alternate line out powerdown. when ?set?, the alternate line out buffer is powered down. pr5 internal clock disable. when ?set?, this bit completely powers down both the analog and digital sections of the cs429 9 -bq . the only way to recover from setting this bit is through a cold re- set (driving the reset# signal active). pr4 ac-link powerdown. when ?set?, the ac link is powered down (bit_clk off). the ac-link can be restarted through a warm reset using the sync signal, or a cold reset using the reset# signal (primary audio codec only). pr3 analog mixer powerdown (vref off). when ?set?, the analog mixer and voltage reference are powered down. when clearing this bit, the anl, adc, and dac bits should be checked before writing any mixer registers. pr2 analog mixer powerdown (vref on). when ?set?, the analog mixer is powered down (the voltage reference is still active). when clearing this bit, the anl bit should be checked before writing any mixer registers. pr1 front dacs powerdown. when ?set?, the dacs are powered down. when clearing this bit, the dac bit should be checked before sending any data to the dacs. pr0 l/r adcs and input mux powerdown. when ?set?, the adcs and the adc input muxes are pow- ered down. when clearing this bit, no valid data will be sent down the ac link until the adc bit goes high. ref voltage reference ready status. when ?set?, indicates the voltage reference is at a nominal level. anl analog ready status. when ?set?, the analog output mixer, input multiplexer, and volume con- trols are ready. when clear, no volume control registers should be written. dac front dac ready status. when ?set?, the dacs are ready to receive data across the ac link. when clear, the dacs will not accept any valid data. adc l/r adc ready status. when ?set?, the adcs are ready to send data across the ac link. when clear, no data will be sent to the controller. default 0000h. this value indicates all blocks are powered on. the lower four bits will change as the cs429 9 -bq finishes an initialization and calibration sequence. the pr[6:0] and the eapd bits are powerdown control for different sections of the cs429 9 -bq as well as external amplifiers. the ref, anl, dac, and adc bits are read-only status bits which, when ?set?, indicate that a particular section of the cs429 9 -bq is ready. after the controller receives the codec ready bit in input slot 0, these status bits must be checked before writing to any mixer registers. see section5, power management , for more information on the powerdown functions. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc ds319-bqpp2 27 cs4299-bq
cs429 9 -bq 28 4.14 extended audio id register (index 28h) id[1:0] codec configuration id. when id[1:0] = 00, the cs429 9 -bq is the primary audio codec. when id[1:0]=01, 10, or 11, the cs429 9 -bq is a secondary audio codec. the state of the id[1:0] bits is determined at power-up from the id[1:0]# pins. amap audio slot mapping. the amap bit indicates whether the optional ac ?97 2.1 compliant ac-link slot to audio dac mapping is supported. this bit is a shadow of the amap bit in the ac mode control register (index 5eh) . the pcm playback and capture slots are mapped according to table8 on page30. vra variable rate pcm audio. the vra bit indicates whether variable rate pcm audio is supported. this bit always returns ? 1 ?, indicating that variable rate pcm audio is available. default x20 1 h. where x is determined by the state of id[1:0]# input pins. the extended audio id reg- ister (index 28h) is a read only register. 4.15 extended audio status/control register (index 2ah) vra enable variable rate audio. when ?set?, the vra bit allows access to the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) . the bit must be ?set? in order to use variable pcm playback or capture rates. the vra bit also serves as a powerdown for the dac and adc src blocks. clearing vra will reset the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) to their default values . the src data path is flushed and the slot request bits for the currently active dac slots will be fixed at ?0?. default 0000h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1 id0 0 0 0 0 amap 0 0 0 0 0 0 0 0 vra d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vra 28 ds319-bqpp2 cs4299-bq
cs429 9 -bq 29 4.16 pcm front dac rate register (index 2ch) sr[15:0] front dac sample rate. the sr[15:0] bits can only be written when the vra bit of the extend- ed audio status/control register (index 2ah) is ?set?. if the vra bit is ?clear?, all writes are ig- nored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vra bit is ?set?, seven standard sample rates are available. if a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in table7. all register read transactions will reflect the actual value stored (column 2 in table7) and not the one attempted to be written. default bb80h. this value corresponds to 48 khz sample rate.. 4.17 pcm l/r adc rate register (index 32h) sr[15:0] left/right adc sample rate. the sr[15:0] bits can only be written when the vra bit of the extended audio status/control register (index 2ah) is ?set?. if the vra bit is ?clear?, all writes are ignored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vra bit is ?set?, seven standard sample rates are available. if a sample rate written to the reg- ister is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in table7. all register read transactions will reflect the actual value stored (column 2 in table7) and not the one attempted to be written. default bb80h. this value corresponds to 48 khz sample rate. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sample rate (hz) sr[15:0] sr[15:12] decode range 8,000 1f40 0 or 1 11,025 2b11 2 16,000 3e80 3 22,050 5622 4 or 5 32,000 7d00 6 or 7 44,100 ac44 8, 9, or ah 48,000 bb80 bh, ch, dh, eh, or fh table 7. standard sample rates d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 ds319-bqpp2 29 cs4299-bq
cs429 9 -bq 30 4.18 ac mode control register (index 5eh) ddm dac direct mode. this bit controls the source to the line and alternate line output drivers. when ?set?, the l/r dacs directly drive the line and alternate line outputs by bypassing the audio mix- er. when ?clear?, the audio mixer is the source for the line and alternate line outputs. amap audio slot mapping. this read/write bit controls whether the cs429 9 -bq responds to the co- dec id based slot mapping as outlined in the ac ?97 2.1 specification. the bit is shadowed in the extended audio id register (index 28h) . refer to table8 for the slot mapping configura- tions. sm[1:0] slot map. the sm[1:0] bits define the slot mapping for the cs429 9 -bq when the amap bit is ?cleared?. refer to table8 for the slot mapping configurations. default 0080h 4.19 misc. crystal control register (index 60h) losm loss of sync mute enable. the losm bit controls the loss of sync mute function. if this bit is ?set?, the cs429 9 -bq will mute all analog outputs for the duration of loss of sync. if this bit is ?cleared?, the mixer will continue to function normally during loss of sync. the cs429 9 -bq expects to sample sync ?high? for 16 consecutive bit_clk periods and then ?low? for 240 consecutive bit_clk periods, otherwise loss of sync becomes true. default 0023h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 ddm amap 0 sm1 sm0 0 0 0 0 slot assignment mode codec id slot map amap slot assignments id1 id0 sm1 sm0 dac, spdif adc l r l r amap mode 0 0 0 x x 1 3 4 3 4 amap mode 1 0 1 x x 1 3 4 3 4 amap mode 2 1 0 x x 1 7 8 7 8 amap mode 3 1 1 x x 1 6 9 6 9 slot map mode 0 x x 0 0 0 3 4 3 4 slot map mode 1 x x 0 1 0 5 6 5 6 slot map mode 2 x x 1 0 0 7 8 7 8 slot map mode 3 x x 1 1 0 9 10 9 10 table 8. slot mapping d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 reserved 0 0 reserved 0 reserved losm 30 ds319-bqpp2 cs4299-bq
cs429 9 -bq 31 4.20 s/pdif control register (index 68h) spen s/pdif enable. the spen bit enables s/pdif data transmission on the s/pdif_out pin. the spen bit routes the left and right channel data from the ac ?97 controller, the digital mix- er, or the digital effects engine to the s/pdif transmitter block. the actual data routed to the s/pdif block is controlled through the amap/sm[1:0] configuration in the ac mode control register (index 5eh) . val validity. the v bit is mapped to the v bit (bit 28) of every sub-frame . if this bit is ?0?, the signal is suitable for conversion or processing. fs sample rate. the fs bit indicates the sampling rate for the s/pdif data. the inverse of this bit is mapped to bit 25 of the channel status block. when the fs bit is ?clear?, the sampling frequency is 48khz. when ?set?, the sampling frequency is 44.1khz. the actual rate at which s/pdif data are being transmitted solely depends on the master clock frequency of the cs429 9 -bq . the fs bit is merely an indicator to the s/pdif receiver. l generation status. the l bit is mapped to bit 15 of the channel status block. for category codes 001xxxx, 0111xxx and 100xxxx, a value of ?0? indicates original material and a value of ?1? indicates a copy of original material. for all other category codes the definition of the l bit is reversed. cc[6:0] category code. the cc[6:0] bits are mapped to bits 8-14 of the channel status block. emph data emphasis. the emph bit is mapped to bit 3 of the channel status block. if the emph bit is ?1?, 50/15us filter pre-emphasis is indicated. if the bit is ?0?, no pre-emphasis is indicated. copy copyright. the copy bit is mapped to bit 3 of the channel status block. if the copy bit is ?1? copyright is not asserted and copying is permitted. /audio audio / non-audio. the /audio bit is mapped to bit 1 of the channel status block. if the /audio bit is ?0?, the data transmitted over s/pdif is assumed to be digital audio. if the /audio bit is ?1?, non-audio data is assumed. pro professional/consumer. the pro bit is mapped to bit 0 of the channel status block. if the pro bit is ?0?, consumer use of the audio control block is indicated. if the bit is ?1?, professional use is indicated. default 0000h for a further discussion of the proper use of the channel status bits see application note an22: overview of digital audio interface data structures [3]. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro ds319-bqpp2 31 cs4299-bq
cs429 9 -bq 32 4.21 vendor id1 register (index 7ch) f[7:0] first character of vendor id. with a value of f[7:0] = 43h, these bits define the ascii ?c? character. s[7:0] second character of vendor id. with a value of s[7:0] = 52h, these bits define the ascii ?r? character. default 4352h. this register contains read-only data. 4.22 vendor id2 register (index 7eh) t[7:0] third character of vendor id. with a value of t[7:0] = 59h, these bits define the ascii ?y? character. did[2:0] device id. with a value of did[2:0] = 011 , these bits specify the audio codec is a cs429 9 . rev[2:0] revision. with a value of rev[2:0] = 001, these bits specify the audio codec revision is ?a?. default 59 3 xh. this register contains read-only data. the two vendor id registers provide a means to determine the manufacturer of the ac?97 audio codec. the first three bytes of the vendor id registers contain the ascii code for the first three letters of crystal (cry). the final byte of the vendor id registers is divided into a device id field and a revision field. table9 lists the currently defined device id?s. table10 lists the current revisions of the cs429 9 -bq . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 0 rev2 rev1 rev0 did[2:0] part name 000 cs4297 001 cs4297a 010 cs4294/cs4298 011 cs4299 100 cs4201 101 cs4205 110 cs4291 111 cs4202 table 9. device id with corresponding part number rev[2:0] revision 001 a 010 b 011 c 100 d, e, f, g, h 101 k 110 l table 10. revision values 32 ds319-bqpp2 cs4299-bq
cs429 9 -bq 33 5. power management 5.1 ac?97 reset modes the cs429 9 -bq supports three reset methods, as defined in the ac?97 specification: cold ac?97 reset , warm ac?97 reset , register ac ?97 reset . a cold reset results in all ac ?97 logic (registers included) initialized to its default state. a warm reset leaves the contents of the ac ?97 register set unaltered. a register reset initializes only the ac?97 registers to their default states. 5.1.1 cold ac?97 reset a cold reset is achieved by asserting reset# for a minimum of 1 s after the power supply rails have stabilized. this is done in accordance with the minimum timing specifications in the ac ?97 seri- al port timing section on page7. once deasserted, all of the cs429 9 -bq registers will be reset to their default power-on states and the bit_clk and sdata_in signals will be reactivated. 5.1.2 warm ac?97 reset a warm reset allows the ac-link to be reactivated without losing information in the cs429 9 -bq reg- isters. a warm reset is required to resume from a d3 hot state, where the ac-link had been halted yet full power had been maintained. a primary codec warm reset is initiated when the sync signal is driven high for at least 1 s and then driven low in the absence of the bit_clk clock signal. the bit_clk clock will not restart until at least 2 nor- mal bit_clk clock periods (162.8ns) after the sync signal is deasserted. a warm reset of the secondary codec is recognized when the primary codec on the ac-link resumes bit_clk genera- tion. the cs429 9 -bq will wait for bit_clk to be stable to restore sdata_in activity and/or s/pdif transmission on the following frame. 5.1.3 register ac?97 reset the third reset mode provides a register reset to the cs429 9 -bq . this is available only when the cs429 9 -bq ac-link is active and the codec ready bit is ?set?. the audio (including extended audio) registers (index 00h - 38h) and the vendor specific registers (index 5ah - 7ah) are reset to their default states by a write of any value to the re- set register (index 00h) . ds319-bqpp2 33 cs4299-bq
cs429 9 -bq 34 5.2 powerdown controls the powerdown control/status register (index26h) controls the power management func- tions. the pr[6:0] bits in this register control the internal powerdown states of the cs429 9 -bq . powerdown control is available for individual sub- sections of the cs429 9 -bq by asserting any prx bit or any combination of prx bits. most power- down states can be resumed by clearing the corre- sponding prx bit. table11 shows the mapping of the power control bits to the functions they man- age. when pr0 is ?set?, the l/r adcs and the input mux are shut down and the adc bit in the power- down control/status register (index 26h) is ?cleared? indicating the adcs are no longer in a ready state. the same is true for the dacs, the an- alog mixers, and the reference voltage (vrefout). when the pr2 or pr3 bit of the mixer is ?cleared?, the mixer section will begin a power-on process, and the corresponding powerdown status bit will be ?set? when the hardware is ready. shutting down the ac-link by ?setting? pr4 causes the primary codec to turn off the bit_clk and drive sdata_in low. it also ignores sync and sdata_out in their normal capacities. either a cold reset or a warm reset is required to restore operation to the cs429 9 -bq . a cold reset will re- store all mixer registers to their power-on default values. a warm reset will not alter the values of any mixer register, except clearing the pr4 bit in powerdown control/status register (index26h) . the pr5 bit powers down all analog and digital subsections of the device. a cold reset is the only way to restore operation to the cs429 9 -bq after a pr5 global powerdown. the cs429 9 -bq does not automatically mute any input or output when the powerdown bits are ?set?. the software driver controlling the ac?97 device must manage muting the input and output analog signals before putting the part into any power man- agement state. the definition of each prx bit may affect a single subsection or a combination of sub- sections within the cs429 9 -bq . table12 on page35 contains the matrix of subsections affected by the respective prx function. table13 on page35 shows the different operating power con- sumptions levels for different powerdown func- tions. pr bit function pr0 l/r adcs and input mux powerdown pr1 front dacs powerdown pr2 analog mixer powerdown (vref on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off)* pr5 internal clock disable pr6 alternate line out powerdown * applies only to primary codec table 11. powerdown pr bit functions 34 ds319-bqpp2 cs4299-bq
cs429 9 -bq 35 pr bit adcs dacs mixer alternate line out analog reference ac link internal clock off pr0 ? pr1 ? pr2 ? ? ? pr3 ? ? ? ? ? pr4 ? pr5 ? ? ? ? ? ? ? pr6 ? table 12. powerdown pr function matrix power state i dvdd (ma) [dvdd=3.3v] i dvdd (ma) [dvdd=5v] i avdd (ma) full power + src?s 29.1 50.2 37.9 full power + s/pdif 1 30.1 49.4 37.9 full power 24.5 43.4 37.9 adcs off (pr0) 21.0 38.1 29.0 dacs off (pr1) 22.1 39.6 31.3 audio off (pr2) 22.1 39.9 10.7 vref off (pr3) 18.9 34.8 45 a ac-link off (pr4) 19.3 35.5 37.9 internal clocks off (pr5) 11 a 27 a 45 a alt line out off (pr6) 24.5 43.4 36.2 reset 11 a 27 a 450 a table 13. power consumption by powerdown mode 1 assuming standard resistive load for transformer coupled coaxial s/pdif output (rload = 292 ohm, dvdd = 3.3 v) (rload = 415 ohm, dvdd = 5 v). general: i dvdds/pdif = i dvdd + dvdd/rload/2 ds319-bqpp2 35 cs4299-bq
cs429 9 -bq 36 6. analog hardware description the analog line-level input hardware consists of four stereo inputs (line_in_l/r, cd_l/gnd/r, video_l/r, and aux_l/r), two selectable mono microphone inputs (mic1 and mic2), and two mono inputs (pc_beep and phone). the an- alog line-level output hardware consists of a mono output (mono_out), and dual stereo line outputs (line_out_l/r and alt_line_out_l/r). this section describes the analog hardware needed to interface with these pins. the designs presented in this section comply with specifications detailed in chapter 17 of the microsoft ? pc design guide- lines [7] (referred to as pc 99). for emi reduction techniques refer to the application note an165: cs4297a/cs4299 emi reduction techniques [5]. 6.1 analog inputs all analog inputs to the cs429 9 -bq , including cd_gnd, should be capacitively coupled to the input pins. unused analog inputs should be tied to- gether and connected through a capacitor to analog ground or tied to the vrefout pin directly. the max- imum allowed voltage for analog inputs, except the microphone input, is 1 v rms . for the microphone input the maximum allowed voltage depends on the selected boost setting. 6.1.1 line-level inputs figure10 shows circuitry for a line-level stereo in- put. replicate this circuit for the line, video and aux inputs. this design attenuates the input by 6db, bringing the signal from the pc 99 specified 2 v rms , to the cs429 9 -bq maximum allowed 1v rms . 6.1.2 cd input the cd line-level input has an extra pin, cd_gnd, providing a pseudo-differential input for both cd_l and cd_r. this pin takes the common -mode noise out of the cd inputs when connected to the cd analog source ground. follow- ing the reference designs in figure11 and figure12 provides extra attenuation of common mode noise coming from the cd-rom drive, thereby producing a higher quality signal. one per- cent resistors are recommended since closely matched resistor values provide better com- mon-mode attenuation of unwanted signals. the circuit shown in figure11 can be used to attenuate a 2 v rms cd input signal by 6 db. the circuit shown in figure12 can be used for a 1 v rms cd in- put signal. 6 . 8 k ? 6 . 8 k ? 1 . 0 f 1 . 0 f r l 6 . 8 k ? 6 . 8 k ? figure 10. line input (replicate for video and aux) (all resistors 1%) 6.8 k ? cd_l cd_com cd_r 1.0 f cd_l cd_r cd_gnd 6.8 k ? 1.0 f 3.4 k ? 6.8 k ? 2.2 f 3.4 k ? 6.8 k ? agnd figure 11. differential 2 v rms cd input 100 ? cd_l cd_com cd_r 1.0 f cd_l cd_r cd_gnd 100 ? 1.0 f 100 ? 47 k ? 2.2 f 47 k ? 47 k ? agnd figure 12. differential 1 v rms cd input 36 ds319-bqpp2 cs4299-bq
cs429 9 -bq 37 6.1.3 microphone inputs figure13 illustrates an input circuit suitable for dy- namic and electret microphones. electret, or phan- tom-powered, microphones use the right channel (ring) of the jack for power. the design also sup- ports the recommended advanced frequency re- sponse for voice recognition as specified in pc 99. note the microphone input to the cs429 9 -bq has an integrated pre-amplifier. using the 20db bit in the microphone volume register (index0eh) the pre-amplifier gain can be set to 0db or 20 db. figure14 shows an external pre-amplifier circuit for an additional 18 db gain. 6.1.4 pc beep input the pc_beep input is useful for mixing the output of the ?beeper? (timer chip), provided in most pcs, with the other audio signals. when the cs429 9 -bq is held in reset, pc_beep is passed directly to the line output. this allows the system sounds or ?beeps? to be available before the ac?97 interface has been activated. figure15 illustrates a typical input circuit for the pc_beep input. if pc_beep is driven from a cmos gate, the 4.7k ? resistor should be tied to analog ground instead of +5va. although this input is described for a low-quality ?beeper?, it is of the same high-quality as all other analog inputs and may be used for other purposes. 0 . 3 3 f 2 2 0 p f n p o 3 . 3 f + 6 . 8 k ? 4 7 k ? m c 3 3 0 7 8 o r m c 3 3 1 7 8 v r e f o u t m i c 1 o r m i c 2 1 f + 0 . 3 3 f x 7 r 2 k ? 4 7 k ? 0 . 1 f 4 7 ? 1 0 0 p f n p o figure 13. microphone input a g n d 4 8 + 5 v a 1 0 0 1 2 5 3 4 2 . 7 c g n d 2 2 0 p f 2 2 0 p f 6 8 a g n d 0 . 0 6 8 f x 7 r a g n d + - a g n d 4 1 8 + 5 v a u 1 a m c 3 3 0 7 8 d 3 2 1 0 f a g n d + 4 7 a g n d + 5 v a 4 7 + - 6 . 8 1 0 f a g n d + 6 5 2 2 0 p f 4 7 k ? u 1 b m c 3 3 0 7 8 d 1 f x 7 r 7 mic1/mic2 k ? k ? k ? k ? k ? k ? 47 k ? figure 14. microphone pre-amplifier 4.7 k ? p c _ b e e p +5va (low noise) or agnd if cmos source pc-beep-bus 47 k ? 2.7 nf x7r 0.1 f x7r agnd figure 15. pc_beep input ds319-bqpp2 37 cs4299-bq
cs429 9 -bq 38 6.1.5 phone input one application of the phone input is to interface to the output of a modem analog front end (afe) device so that modem dialing signals and protocol negotiations may be monitored through the audio system. figure16 shows a design for a modem connection where the output is fed from the cs429 9 -bq mono_out pin through a divider. the divider ratio shown does not attenuate the sig- nal, providing an output voltage of 1 v rms . if a lower output voltage is desired, the resistors can be replaced with appropriate values, as long as the to- tal load on the output is kept greater than 10 k ? . the phone input is divided by 6 db to accommo- date a line-level source of 2 v rms . 6.2 analog outputs the analog line-level output section provides two stereo outputs and a mono output. the line_out_l/r, alt_line_out_l/r, and mono_out pins require 680pf to 1000pf npo capacitors between the corresponding pin and ana- log ground. each analog output is dc-biased up to the vrefout signal reference, nominally 2.3v. this requires the outputs be ac-coupled to external cir- cuitry (ac load must be greater than 10k ? ) or dc coupled to a buffer op-amp biased at vrefout. 6.2.1 stereo outputs see figure18 for a line-level stereo output refer- ence design. see figure17 for a recommended headphone stereo output reference design. 6.2.2 mono output the mono output, mono_out, can be either a sum of the left and right output channels, attenuat- ed by 6db to prevent clipping at full scale, or the selected mic signal. the mono out channel can drive the pc internal mono speaker using an appro- priate buffer circuit phone mono_out phone mono_out 6.8 k ? 1.0 f 0 ? 6.8 k ? 1.0 f 47 k ? agnd agnd 1000 pf figure 16. modem connection alt_line_out_r alt_line_out_l 27 k ? 1000 pf npo agnd 3 2 1 220 f elec 220 f elec + + 1000 pf npo 27 k ? 47 k ? agnd 22 pf npo 39 k ? 5 6 7 22 pf npo 39 k ? + - + - tda1308 vrefout 10 ? 1/4 watt 10 ? 1/4 watt 47 k ? headphone out figure 17. alternate line output as headphone output a g n d a l t _ l i n e _ o u t _ r 2 7 k ? 1 0 0 0 p f n p o 1 0 0 0 p f n p o 1 2 3 4 a g n d 0 . 1 f y 5 v 2 2 0 f + 5 - 3 9 k ? 1 2 3 4 + 3 - 2 2 p f n p o 2 2 p f n p o 6 2 7 1 t d a 1 3 0 8 t d a 1 3 0 8 a l t _ l i n e _ o u t _ l v r e f o u t + e l e c 1 / 4 w a t t 1 0 ? h p _ o u t _ r 2 2 0 f + e l e c 1 / 4 w a t t 1 0 ? h p _ o u t _ l 4 7 k ? 1 3 4 a g n d 2 1 f figure 18. stereo output 38 ds319-bqpp2 cs4299-bq
cs429 9 -bq 39 6.3 miscellaneous analog signals the aflt1 and aflt2 pins must have a 1000pf npo capacitor to analog ground. these capacitors provide a single-pole low-pass filter at the inputs to the adcs. this makes low-pass filters at each ana- log input pin unnecessary. the refflt pin must have a 1 f and a 0.1 f ca- pacitor connected to analog ground with a short, wide trace to this pin (see figure21 in section8, grounding and layout , for an example). the 1 f capacitor must not be replaced with any value high- er than 1 f. no other connection should be made, as any coupling onto this pin will degrade the ana- log performance of the cs429 9 -bq . likewise, dig- ital signals should be kept away from refflt for similar reasons. the vrefout pin is typically 2.3v and provides a common mode signal for single-supply external circuits. vrefout only supports light dc loads and should be buffered if ac loading is needed. for typical use the vrefout pin should have a 1 f and a 0.1 f capacitor connected to analog ground. 6.4 power supplies the power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog per- formance. the analog power pins, avdd1 and avdd2, supply power to all the analog circuitry on the cs429 9 -bq . the +5 v analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 v supply. this helps iso- late the analog circuitry from noise typically found on +5v digital supplies. a typical voltage regula- tor circuit for analog power using a mc78m05cdt +5 v regulator is shown in figure19. the digital power pins, dvdd1 and dvdd2, should be connected to the same digital supply as the controller ac-link interface. the dig- ital interface on the cs429 9 -bq may operate at ei- ther +3.3 v or +5 v and proper connection of these pins will depend on the digital power supply of the controller. 6.5 reference design see section11 for a cs429 9 -bq reference design. figure 19. voltage regulator + 1 2 v d a g n d d g n d + 5 v a 0 . 1 f y 5 v 1 0 f e l e c + 1 0 f e l e c + m c 7 8 m 0 5 c d t o u t 3 g n d 2 i n 1 0 . 1 f y 5 v ds319-bqpp2 39 cs4299-bq
cs429 9 -bq 40 7. sony/philips digital interface (s/pdif) the s/pdif digital output is used to interface the cs429 9 -bq to consumer audio equipment external to the pc. this output provides an interface for storing digital audio data or playing digital audio data to digital speakers. figure20 illustrates the circuits necessary for implementing the iec-958 optical or consumer interface. for further informa- tion on s/pdif operation see application note an22: overview of digital audio interface data structures [3] . for further information on s/pdif recommended transformers see application note an134: aes and s/pdif recommended trans- formers [4]. 8. grounding and layout figure21 on page41 shows the conceptual layout for the cs429 9 -bq . the decoupling capacitors should be located physically as close to the pins as possible. also note the connection of the refflt decoupling capacitors to the ground return trace connected directly to the ground return pin, avss1. it is strongly recommended that separate analog and digital ground planes be used. separate ground planes keep digital noise and return currents from modulating the cs429 9 -bq ground potential and degrading performance. the digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections of the cs429 9 -bq and any other external analog circuitry. all analog components and traces should be located over the analog ground plane and all dig- ital components and traces should be located over the digital ground plane. the common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located under the cs429 9 -bq . the ac-link digital interface con- nection traces should be routed such that the digital ground plane lies underneath these signals (on the internal ground layer). this applies along the entire length of these traces from the ac?97 controller to the cs429 9 -bq . refer to the application note an18: layout and design rules for data converters and other mixed signal devices [2] for more information on layout and design rules. 1 2 3 4 5 6 0.1 f r 2 r 1 j1 dgnd dvdd r 1 r 2 spdif_out s/pdif_out totx-173 spdif_out +5v_pci dgnd 8.2 k ? dgnd dgnd 3.3v 247.5 ? 107.6 ? 5v 375 ? 93.75 ? t 1 figure 20. s/pdif output 40 ds319-bqpp2 cs4299-bq
cs429 9 -bq 41 analog ground p i n 1 0 . 1 f 1 0 0 0 p f n p o 1 f 0 . 1 f y 5 v 0 . 1 f y 5 v y 5 v 0 . 1 f y 5 v a v d d 2 a v s s 2 aflt2 r e f f l t a v s s 1 a v d d 1 d v d d 2 aflt1 digital ground d v s s 2 d v s s 1 d v d d 1 v r e f o u t t o v i a via to +5va via to +5va via to analog ground via to analog ground via to digital ground via to +5vd or +3.3vd via to +5vd or +3.3vd figure 21. conceptual layout for the cs429 9 -bq ds319-bqpp2 41 cs4299-bq
cs429 9 -bq 42 9. pin descriptions c d _ a u x _ v i d e o _ c d _ m i c p h o n a u x _ v i d e o _ c d _ g n m i c l i n e _ i n _ l i n e _ i n _ l l l r 2 e r r d 1 l r b p c f g l i n e _ o u t _ l f l t i aflt1 r e f f l t l i n e _ o u t _ r f l t o f l t 3 d aflt2 vrefout a v s s 1 avdd1 n c a v d d 2 m o n o _ o u t 6 2 4 8 1 0 1 3 5 7 9 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 31 35 33 29 27 36 34 32 30 28 26 25 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 c s 4 2 9 9 - x q bit_clk xtl_in dvss1 s d a t a _ i n sync dvdd1 xtl_out s d a t a _ o u t dvdd2 r e s e t # p c _ b e e p d v s s 2 a l t _ l i n e _ o u t _ r a l t _ l i n e _ o u t _ l n c e a p d i d 0 # s / p d i f _ o u t i d 1 # n c a v s s 2 ( 4 8 - p i n l qfp) figure 22. pin locations for the cs4299 -bq 42 ds319-bqpp2 cs4299-bq
cs429 9 -bq 43 audio i/o pc_beep - analog mono source, input, pin 12 the pc_beep input is intended to allow the pc system post (power on self-test) tones to pass through to the audio subsystem. the pc_beep input has two connections: the first connection is to the analog output mixer, the second connection is directly to the line_out stereo outputs. while the reset# pin is actively being asserted and the bcfg pin is left floating, the pc_beep bypass path to the line_out outputs is enabled. while the cs429 9 -bq is in normal operation mode, with reset# deasserted or bcfg grounded, pc_beep is a monophonic source to the analog output mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. phone - analog mono source, input, pin 13 this analog input is a monophonic source to the analog output mixer. it is intended to be used as a modem subsystem input to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic1 - analog mono source, input, pin 21 this analog input is a monophonic source to the analog output mixer. it is intended to be used as a desktop microphone connection to the audio subsystem. the cs429 9 -bq internal mixer's microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic2 - analog mono source, input, pin 22 this analog input is a monophonic source to the analog output mixer. it is intended to be used as an alternate microphone connection to the audio subsystem. the cs429 9 -bq internal mixer's microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. line_in_l, line_in_r - analog line source, inputs, pins 23 and 24 these inputs form a stereo input pair to the cs429 9 -bq . the maximum allowable input is 1v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. cd_l, cd_r - analog cd source, inputs, pins 18 and 20 these inputs form a stereo input pair to the cs429 9 -bq . it is intended to be used for the red book cd audio connection to the audio subsystem. the maximum allowable input is 1v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. cd_gnd - analog cd common source, input, pin 19 this analog input is used to remove common mode noise from red book cd audio signals. the impedance on the input signal path should be one half the impedance on the cd_l and cd_r input paths. this pin requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. ds319-bqpp2 43 cs4299-bq
cs429 9 -bq 44 video_l, video_r - analog video audio source, inputs, pins 16 and 17 these inputs form a stereo input pair to the cs429 9 -bq . it is intended to be used for the audio signal output of a video device. the maximum allowable input is 1v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. aux_l, aux_r - analog auxiliary source, inputs, pins 14 and 15 these inputs form a stereo input pair to the cs429 9 -bq . the maximum allowable input is 1v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. line_out_l, line_out_r - analog line-level, outputs, pins 35 and 36 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 1v rms (sinusoidal). these outputs are internally biased at the vrefout voltage reference and require either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage . these pins need a 680-1000 pf npo capacitor attached to analog ground. alt_line_out_l, alt _line_out_r - analog alternate line-level, outputs, pins 39 and 41 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 1v rms (sinusoidal). these outputs are internally biased at the vrefout voltage reference and require either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage . these pins need a 680-1000 pf npo capacitor attached to analog ground. mono_out - analog mono line-level, output, pin 37 this signal is an analog output from the stereo-to-mono mixer or mic1/2. the full-scale output voltage for this output is nominally 1 v rms (sinusoidal). this output is internally biased at the vrefout voltage reference and requires either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage. this pin needs a 680-1000 pf npo capacitor attached to analog ground. clock and configuration xtl_in - crystal input/clock input, pin 2 in primary mode this pin requires either a 24.576 mhz crystal, with the other pin attached to xtl_out, or an external cmos clock. the crystal frequency must be 24.576 mhz and designed for fundamental mode, parallel resonance operation. if an external cmos clock is used to drive this pin, it must run at 24.576 mhz. in secondary mode all timing is derived from the bit_clk input signal and this pin should be left floating. xtl_out - crystal output, pin 3 this pin is used when a crystal is placed between xtl_out and xlt_in. if an external 24.576 mhz clock is used on xtl_in, this pin must be left floating with no traces or components connected to it. in secondary mode this pin should be left floating. id1#,id0# - codec id, inputs, pins 45 and 46 these pins select the codec id and mode of operation for the cs429 9 -bq . they are only sampled after the rising edge of reset#. these pins are internally pulled up to the digital supply voltage and should be left floating for logic ?0? or tied to digital ground for logic ?1?. when both pins are left floating the cs429 9 -bq is the primary codec. if either or both pins are tied to ground the cs429 9 -bq is a secondary codec. 44 ds319-bqpp2 cs4299-bq
cs429 9 -bq 45 analog reference, filters, and configuration refflt - internal reference voltage, input, pin 27 this signal is the voltage reference used internal to the cs429 9 -bq . a 0.1 f and a 1.0 f (must not be larger than 1 f) capacitor with short, wide traces must be connected to this pin. no other connections should be made to this pin. vrefout - voltage reference, output, pin 28 all analog inputs and outputs are centered around vrefout, nominally 2.3 volts. this pin may be used to level shift external circuitry. this pin cannot drive any dc loads, thus any external loading must be buffered. aflt1 - left adc channel antialiasing filter, input, pin 29 this pin needs a 1000 pf npo capacitor connected to analog ground. aflt2 - right adc channel antialiasing filter, input, pin 30 this pin needs a 1000 pf npo capacitor connected to analog ground. flti, flto - 3d filter, input, pin 33 and 34 a 1000 pf capacitor must be connected between flti and flto if the 3d function is used. flt3d - 3d filter, input, pin 32 a 0.01 f capacitor must be connected from this pin to agnd if the 3d function is used. bcfg - beep configuration, input, pin 31 this pin is the configuration control for the pc_beep bypass path. if this pin is grounded, the bypass path is disabled. if this pin is left floating, the pc_beep bypass path is enabled. misc. digital interfaces s/pdif_out - sony/philips digital interface, output, pin 48 this pin generates the s/pdif digital output from the cs429 9 -bq when the spen bit in the s/pdif control register (index 68h) is ?set?. this output may be used to directly drive a resistive divider and coupling transformer to an rca-type connector for use with consumer audio equipment. eapd - external amplifier powerdown, output, pin 47 this pin is used to control the powerdown state of an audio amplifier external to the cs429 9 -bq . the output is controlled by the eapd bit in the powerdown ctrl/stat register (index 26h) . it is driven as a normal cmos output and defaults low (?0?) upon power-up. ds319-bqpp2 45 cs4299-bq
cs429 9 -bq 46 ac-link reset# - ac?97 chip reset, input, pin 11 this active low signal is the asynchronous cold reset input to the cs429 9 -bq . the cs429 9 -bq must be reset before it can enter normal operating mode. sync - ac-link serial port sync pulse, input, pin 10 this signal is the serial port timing signal for the ac-link. its period is the reciprocal of the maximum sample rate, 48khz. the signal is generated by the controller, synchronous to bit_clk. sync is an asynchronous input when the cs429 9 -bq is configured as a primary audio codec and is in a pr4 powerdown state. a series terminating resistor of 47 ? should be connected on the signal near the sync source. bit_clk - ac-link serial port master clock, input/output, pin 6 this input/output signal controls the master clock timing for the ac-link. in primary mode, this signal is a 12.288 mhz output clock derived from a 24.576 mhz crystal on the xtl_in input clock. when the cs429 9 -bq is in secondary mode, this signal is an input which controls the ac-link serial interface and generates all internal clocking including the ac-link serial interface timing and the analog sampling clocks. a series terminating resistor of 47 ? should be connected on this signal close to the cs429 9 -bq in primary mode or close to the bit_clk source in secondary mode. sdata_out - ac-link serial data input stream to ac?97, input, pin 5 this input signal receives the control information and digital audio output streams. the data is clocked into the cs429 9 -bq on the falling edge of bit_clk. a series terminating resistor of 47 ? should be connected on this signal near the controller. sdata_in - ac-link serial data output stream from ac?97, output, pin 8 this output signal transmits the status information and digital audio input streams from the adcs. the data is clocked out of the cs429 9 -bq on the rising edge of bit_clk. a series terminating resistor of 47 ? should be connected on this signal as close to the cs429 9 -bq as possible. power supplies dvdd1, dvdd2 - digital supply voltage, pins 1 and 9 digital supply voltage for the ac-link section of the cs429 9 -bq . these pins can be tied to +5v digital or to +3.3 v digital. the cs429 9 -bq and controller ac-link should share a common digital supply dvss1, dvss2 - digital ground, pins 4 and 7 digital ground connection for the ac-link section of the cs429 9 -bq . these pins should be isolated from analog ground currents. avdd1, avdd2 - analog supply voltage, pins 25 and 38 analog supply voltage for the analog and mixed signal sections of the cs429 9 -bq . these pins must be tied to the analog +5 v power supply. it is strongly recommended that +5 v be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. avss1, avss2 - analog ground, pins 26 and 42 ground connection for the analog, mixed signal, and substrate sections of the cs429 9 -bq . these pins should be isolated from digital ground currents. 46 ds319-bqpp2 cs4299-bq
cs429 9 -bq 47 10. parameter and term definitions ac?97 specification refers to the audio codec?97 component specification ver 2.1 published by the intel ? corporation [6]. ac?97 controller or controller refers to the control chip which interfaces to the audio codec ac-link. this has been also called dc?97 for digital controller ?97 [6]. ac?97 registers or codec registers refers to the 64-field register map defined in the ac?97 specification. adc refers to a single analog-to-digital converter in the cs429 9 -bq . ?adcs? refers to the stereo pair of analog-to-digital converters. the cs429 9 -bq adcs have 18-bit resolution. codec refers to the chip containing the adcs, dacs, and analog mixer. in this data sheet, the codec is the cs429 9 -bq . dac refers to a single digital-to-analog converter in the cs429 9 -bq . ?dacs? refers to the stereo pair of digital-to-analog converters. the cs429 9 -bq dacs have 20-bit resolution. db fs a db fs is defined as db relative to full-scale. the ?a? indicates an a weighting filter was used. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. dynamic range (dr) dr is the ratio of the rms full-scale signal level divided by the rms sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a. fft fast fourier transform. frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. fs sampling frequency. interchannel gain mismatch for the adcs, the difference in input voltage to get an equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units are in db. ds319-bqpp2 47 cs4299-bq
cs429 9 -bq 48 interchannel isolation the amount of 1 khz signal present on the output of the grounded ac-coupled line input channel with 1 khz, 0 db, signal present on the other line input channel. units are in db. line-level refers to a consumer equipment compatible, voltage driven interface. the term implies a low driver impedance and a minimum 10 k ? load impedance. paths a-d: analog in, through the adcs, onto the serial link. d-a: serial interface inputs through the dacs to the analog output. a-a: analog in to analog out (analog mixer). pc 99 refers to the pc 99 system design guide published by the microsoft ? corporation [7]. pll phase lock loop. circuitry for generating a desired clock from an external clock source. resolution the number of bits in the output words to the dacs, and in the input words to the adcs. signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinusoidal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. s/pdif sony/phillips digital interface. this interface was established as a means of digitally interconnecting consumer audio equipment. the documentation for s/pdif has been superseded by the iec-958 consumer digital interface document. src sample rate converter. converts data derived at one sample rate to a differing sample rate. the cs429 9 -bq operates at a fixed sample frequency of 48 khz. the internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 khz. total harmonic distortion plus noise (thd+n) thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. it is tested using a -3 db fs input signal and is measured over a 20 hz to 20 khz bandwidth with units in db fs. 48 ds319-bqpp2 cs4299-bq
cs429 9 -bq 49 11. reference design r21 6.8k r16 6.8k c33 22pf npo c34 22pf npo c7 1uf y5v c10 0.1uf x7r j1 2x1hdr-sn/pb 1 2 c20 1uf y5v r14 6.8k c11 0.1uf x7r c4 0.1uf x7r r1 47k r6 6.8k c8 0.1uf x7r j4 phono-1/8 4 3 5 2 1 c5 0.1uf x7r c23 0.1uf x7r c22 1uf y5v r4 6.8k j5 phono-1/8 4 3 5 2 1 c9 0.1uf x7r c24 1uf y5v c3 10uf elec + r8 47 r3 6.8k c18 1000pf npo y1 24.576 mhz j3 4x1hdr-au 1 2 3 4 r10 100k c21 1uf y5v c6 10uf elec + c12 1uf y5v j2 4x1hdr-au 1 2 3 4 r9 100k c31 0.1uf x7r c19 1000pf npo u3 cs4299 line_out_r 36 mono_out 37 avdd2 38 alt_line_out_l 39 nc7 44 alt_line_out_r 41 avss2 42 nc6 43 nc5 40 flto 34 flti 33 flt3d 32 bcfg 31 dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 sync 10 dvdd2 9 reset# 11 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 24 avdd1 25 avss1 26 refflt 27 vrefout 28 aflt1 29 aflt2 30 s/pdif_out 48 eapd 47 id1# 46 id0# 45 line_out_l 35 r5 6.8k j6 totx-173 1 2 3 4 5 6 r15 6.8k c30 1uf y5v c13 1uf y5v r7 47 c2 2700pf x7r 60 mil trace gnd_tie c29 1000pf npo r11 100k c1 0.1uf x7r c28 0.01uf x7r u1 mc78m05acdt out 3 gnd 2 in 1 j7 phono-1/8 4 3 5 2 1 c27 1000pf npo c14 1uf y5v r17 6.8k c26 1000pf npo r20 100 r19 1.5k c25 0.1uf x7r r18 2.2k c15 10uf elec + c17 10uf elec + c32 10uf elec + r2 6.8k r12 220k c16 1uf y5v r13 220k agnd agnd agnd agnd dgnd agnd agnd dgnd agnd agnd dgnd +5va +12v agnd agnd +3.3vd agnd agnd dgnd agnd agnd agnd agnd agnd agnd +5va +5vd dgnd dgnd dgnd abitclk asdin async asdout arst# pc speaker in cd in mic in aux in line in line out tie at one point only under the codec ac link pci audio controller or ich controller (50 ppm) s/pdif out f i g u r e 2 3 . c s 4 2 9 9 r e f e r e n c e d e s i g n ds319-bqpp2 49 cs4299-bq
cs429 9 -bq 50 12. references 1) cirrus logic, audio quality measurement specification , version1.0, 1997 http://www.cirrus.com/products/papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version6.0, february1998 3) cirrus logic, an22: overview of digital audio interface data structures , version2.0, february1998 4) cirrus logic, an134: aes and s/pdif recommended transformers , version2, april1999 5) cirrus logic, an165: cs4297a/cs4299 emi reduction techniques , version1.0, september1999 6) intel ? , audio codec ?97 component specification , revision2.1, may1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm 7) microsoft ? , pc 99 system design guide , version1.0, july 1999 http://www.microsoft.com/hwdev/desguid/ 8) intel ? 82801aa (ich) and 82801ab (ich0) i/o controller hub , june 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm 50 ds319-bqpp2 cs4299-bq
cs429 9 -bq 51 13. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a ds319-bqpp2 51 cs4299-bq

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